/* SPDX-License-Identifier: GPL-2.0 */
/*
 * The NAU8325 is a stereo high efficiency filter-free Class-D audio
 * amplifier driver.
 *
 * Copyright 2020 Nuvoton Technology Crop.
 * Author: Seven Lee <wtli@nuvoton.com>
 */

#ifndef __NAU8325_H__
#define __NAU8325_H__

#define NAU8325_REG_HARDWARE_RST		0x00
#define NAU8325_REG_SOFTWARE_RST		0x01
#define NAU8325_REG_DEVICE_ID			0x02
#define NAU8325_REG_CLK_CTRL			0x03
#define NAU8325_REG_ENA_CTRL			0x04
#define NAU8325_REG_INTERRUPT_CTRL		0x05
#define NAU8325_REG_INT_CLR_STATUS		0x06
#define NAU8325_REG_IRQOUT				0x09
#define NAU8325_REG_IO_CTRL				0x0a
#define NAU8325_REG_I2S_PCM_CTRL0		0x0b
#define NAU8325_REG_TDM_CTRL			0x0c
#define NAU8325_REG_I2S_PCM_CTRL1		0x0d
#define NAU8325_REG_I2S_PCM_CTRL2		0x0e
#define NAU8325_REG_TIME_SLOT			0x0f
#define NAU8325_REG_HPF_CTRL			0x11
#define NAU8325_REG_MUTE_CTRL			0x12
#define NAU8325_REG_DAC_VOLUME			0x13
#define NAU8325_REG_DEBUG_READ1			0x1d
#define NAU8325_REG_DEBUG_READ2			0x1f
#define NAU8325_REG_DEBUG_READ3			0x22
#define NAU8325_REG_DAC_CTRL1			0x29
#define NAU8325_REG_DAC_CTRL2			0x2a
#define NAU8325_REG_ALC_CTRL1			0x2c
#define NAU8325_REG_ALC_CTRL2			0x2d
#define NAU8325_REG_ALC_CTRL3			0x2e
#define NAU8325_REG_ALC_CTRL4			0x2f
#define NAU8325_REG_CLK_DET_CTRL		0x40
#define NAU8325_REG_TEST_STATUS			0x49
#define NAU8325_REG_ANALOG_READ			0x4a
#define NAU8325_REG_MIXER_CTRL			0x50
#define NAU8325_REG_MISC_CTRL			0x55
#define NAU8325_REG_BIAS_ADJ			0x60
#define NAU8325_REG_ANALOG_CONTROL_1	0x61
#define NAU8325_REG_ANALOG_CONTROL_2	0x62
#define NAU8325_REG_ANALOG_CONTROL_3	0x63
#define NAU8325_REG_ANALOG_CONTROL_4	0x64
#define NAU8325_REG_ANALOG_CONTROL_5	0x65
#define NAU8325_REG_ANALOG_CONTROL_6	0x66
#define NAU8325_REG_CLIP_CTRL			0x69
#define NAU8325_REG_RDAC				0x73
#define NAU8325_REG_MAX					NAU8325_REG_RDAC

/* 16-bit control register address, and 16-bits control register data */
#define NAU8325_REG_ADDR_LEN			16
#define NAU8325_REG_DATA_LEN			16


/* CLK_CTRL (0x03) */
#define NAU8325_CLK_DAC_SRC_SFT	12	//4
#define NAU8325_CLK_DAC_SRC_MASK	(0x3 << NAU8325_CLK_DAC_SRC_SFT)
#define NAU8325_MCLK_SRC_MASK	0x7

#define NAU8325_CLK_MUL_SRC_SFT	6
#define NAU8325_CLK_MUL_SRC_MASK	(0x3 << NAU8325_CLK_MUL_SRC_SFT)
#define NAU8325_MCLK_SEL_SFT		8
#define NAU8325_MCLK_SEL_MASK	(0x7 << NAU8325_MCLK_SEL_SFT)

/* ENA_CTRL (0x04) */
#define NAU8325_DAC_LEFT_CH_EN_SFT	3
#define NAU8325_DAC_LEFT_CH_EN	(0x1 << NAU8325_DAC_LEFT_CH_EN_SFT)
#define NAU8325_DAC_RIGHT_CH_EN_SFT	2
#define NAU8325_DAC_RIGHT_CH_EN		(0x1 << NAU8325_DAC_RIGHT_CH_EN_SFT)

/* INTERRUPT_CTRL (0x05) */
#define NAU8325_WD_INT_MASK_SFT	14
#define NAU8325_WD_INT_MASK		(0x1 << NAU8325_WD_INT_MASK_SFT)
#define NAU8325_DSP2I2C_INT_MASK_SFT	13
#define NAU8325_DSP2I2C_INT_MASK	(0x1 << NAU8325_DSP2I2C_INT_MASK_SFT)
#define NAU8325_ARP_DWN_INT_MASK_SFT	12
#define NAU8325_ARP_DWN_INT_MASK	(0x1 << NAU8325_ARP_DWN_INT_MASK_SFT)
#define NAU8325_CLIP_INT_MASK_SFT	11
#define NAU8325_CLIP_INT_MASK		(0x1 << NAU8325_CLIP_INT_MASK_SFT)
#define NAU8325_LVD_INT_MASK_SFT	10
#define NAU8325_LVD_INT_MASK		(0x1 << NAU8325_LVD_INT_MASK_SFT)
#define NAU8325_OVP_INT_MASK_SFT	9
#define NAU8325_OVP_INT_MASK		(0x1 << NAU8325_OVP_INT_MASK_SFT)
#define NAU8325_PWR_INT_DIS_SFT	8
#define NAU8325_PWR_INT_DIS		(0x1 << NAU8325_PWR_INT_DIS_SFT)
#define NAU8325_WD_INT_DIS_SFT	6
#define NAU8325_WD_INT_DIS		(0x1 << NAU8325_WD_INT_DIS_SFT)
#define NAU8325_DSP2I2C_INT_DIS_SFT	5
#define NAU8325_DSP2I2C_INT_DIS	(0x1 << NAU8325_DSP2I2C_INT_DIS_SFT)
#define NAU8325_ARP_DWN_INT_DIS_SFT	4
#define NAU8325_ARP_DWN_INT_DIS	(0x1 << NAU8325_ARP_DWN_INT_DIS_SFT)
#define NAU8325_CLIP_INT_DIS_SFT	3
#define NAU8325_CLIP_INT_DIS		(0x1 << NAU8325_CLIP_INT_DIS_SFT)
#define NAU8325_LVD_INT_DIS_SFT	2
#define NAU8325_LVD_INT_DIS		(0x1 << NAU8325_LVD_INT_DIS_SFT)
#define NAU8325_OVP_INT_DIS_SFT	1
#define NAU8325_OVP_INT_DIS		(0x1 << NAU8325_OVP_INT_DIS_SFT)
#define NAU8325_PWR_INT_MASK		0x1

/* INT_CLR_STATUS (0x06) */
#define NAU8325_INT_STATUS_MASK	0x7ff
#define NAU8325_INT_STATUS_WD	(0x1 << 6)
#define NAU8325_INT_STATUS_DSP2I2C	(0x1 << 5)
#define NAU8325_INT_STATUS_ARP_DWN	(0x1 << 4)
#define NAU8325_INT_STATUS_CLIP	(0x1 << 3)
#define NAU8325_INT_STATUS_LVD	(0x1 << 2)
#define NAU8325_INT_STATUS_OVP	(0x1 << 1)
#define NAU8325_INT_STATUS_PWR	0x1

/* SAR_CTRL1 (0x07) */
#define NAU8325_SAR_TRACKING_GAIN_SFT	11
#define NAU8325_SAR_TRACKING_GAIN_MASK	(0x7 << NAU8325_SAR_TRACKING_GAIN_SFT)
#define NAU8325_SAR_COMPARE_TIME_SFT	5
#define NAU8325_SAR_COMPARE_TIME_MASK	(0x3 << NAU8325_SAR_COMPARE_TIME_SFT)
#define NAU8325_SAR_SAMPLING_TIME_SFT	2
#define NAU8325_SAR_SAMPLING_TIME_MASK	(0x3 << NAU8325_SAR_SAMPLING_TIME_SFT)
#define NAU8325_SAR_ENA_SFT			0
#define NAU8325_SAR_ENA_EN			(0x1 << NAU8325_SAR_ENA_SFT)

/* IO_CTRL (0x0a) */
#define NAU8325_IRQ_PL_SFT		15
#define NAU8325_IRQ_PL_ACT_HIGH	(0x1 << NAU8325_IRQ_PL_SFT)
#define NAU8325_IRQ_DS_SFT		12
#define NAU8325_IRQ_DS_HIGH		(0x1 << NAU8325_IRQ_DS_SFT)
#define NAU8325_IRQ_OUTPUT_SFT 	11
#define NAU8325_IRQ_OUTPUT_EN 	(0x1 << NAU8325_IRQ_OUTPUT_SFT)
#define NAU8325_BCLK_DS_SFT 		2
#define NAU8325_BCLK_DS_EN 		(0x1 << NAU8325_BCLK_DS_SFT)
#define NAU8325_LRC_DS_SFT 		1
#define NAU8325_LRC_DS_EN 		(0x1 << NAU8325_LRC_DS_SFT)
#define NAU8325_ADCDAT_DS_SFT	0
#define NAU8325_ADCDAT_DS_EN 	0x1

/* I2S_PCM_CTRL0	 (0x0b) */
#define NAU8325_DAC_SEL_AGC_SFT	13
#define NAU8325_DAC_SEL_AGC_MASK	(0x7 << NAU8325_DAC_SEL_AGC_SFT)
#define NAU8325_DAC_SEL_SFT		10
#define NAU8325_DAC_SEL_MASK		(0x7 << NAU8325_DAC_SEL_SFT)

/* TDM_CTRL (0x0c) */
#define NAU8325_TDM_SFT		15
#define NAU8325_TDM_EN		(0x1 << NAU8325_TDM_SFT)
#define NAU8325_PINGPONG_SFT		13
#define NAU8325_PINGPONG_EN		(0x1 << NAU8325_PINGPONG_SFT)
#define NAU8325_ADC_ALC_SEL_SFT	6
#define NAU8325_ADC_ALC_SEL_MASK	(0xf << NAU8325_ADC_ALC_SEL_SFT)
#define NAU8325_ADC_I_SEL_SFT		3
#define NAU8325_ADC_I_SEL_MASK	(0x7 << NAU8325_ADC_I_SEL_SFT)
#define NAU8325_ADC_V_SEL_SFT	0
#define NAU8325_ADC_V_SEL_MASK	0x7

/* I2S_PCM_CTRL1 (0x0d) */
#define NAU8325_I2S_BP_SFT		7
#define NAU8325_I2S_BP_MASK		(0x1 << NAU8325_I2S_BP_SFT)
#define NAU8325_I2S_BP_INV		(0x1 << NAU8325_I2S_BP_SFT)
#define NAU8325_I2S_PCMB_SFT		6
#define NAU8325_I2S_PCMB_EN		(0x1 << NAU8325_I2S_PCMB_SFT)
#define NAU8325_I2S_DL_SFT		2
#define NAU8325_I2S_DL_MASK		(0x3 << NAU8325_I2S_DL_SFT)
#define NAU8325_I2S_DL_16		(0x0 << NAU8325_I2S_DL_SFT)
#define NAU8325_I2S_DL_20		(0x1 << NAU8325_I2S_DL_SFT)
#define NAU8325_I2S_DL_24		(0x2 << NAU8325_I2S_DL_SFT)
#define NAU8325_I2S_DL_32		(0x3 << NAU8325_I2S_DL_SFT)
#define NAU8325_I2S_DF_MASK		0x3
#define NAU8325_I2S_DF_RIGTH		0x0
#define NAU8325_I2S_DF_LEFT		0x1
#define NAU8325_I2S_DF_I2S		0x2
#define NAU8325_I2S_DF_PCM_AB	0x3

/* I2S_PCM_CTRL2 (0x0e) */
#define NAU8325_SOFT_MUTE_SFT	15
#define NAU8325_SOFT_MUTE		(1 << NAU8325_SOFT_MUTE_SFT)

#define NAU8325_I2S_LRC_DIV_SFT	12
#define NAU8325_I2S_LRC_DIV_MASK	(0x3 << NAU8325_I2S_LRC_DIV_SFT)
#define NAU8325_I2S_ADCDAT_OE_SFT	4
#define NAU8325_I2S_ADCDAT_OE_MASK	(1 << NAU8325_I2S_ADCDAT_OE_SFT)
#define NAU8325_I2S_ADCDAT_OE_EN	(0 << NAU8325_I2S_ADCDAT_OE_SFT)
#define NAU8325_I2S_ADCDAT_OE_DIS	(1 << NAU8325_I2S_ADCDAT_OE_SFT)
#define NAU8325_I2S_MS_SFT		3
#define NAU8325_I2S_MS_MASK		(0x1 << NAU8325_I2S_MS_SFT)
#define NAU8325_I2S_MS_MASTER	(0x1 << NAU8325_I2S_MS_SFT)
#define NAU8325_I2S_BLK_DIV_MASK	0x7

/* DAC_VOLUME (0x13) */
#define NAU8325_DAC_VOLUME_L_SFT		8
#define NAU8325_DAC_VOLUME_L_EN		(0xff << NAU8325_DAC_VOLUME_L_SFT)
#define NAU8325_DAC_VOLUME_R_SFT		0
#define NAU8325_DAC_VOLUME_R_EN		(0xff << NAU8325_DAC_VOLUME_R_SFT)
#define NAU8325_DAC_VOL_MAX		0xff

/* ADC_VOL_CTRL (0x14) */
#define NAU8325_ADC_GAIN_L_SFT	8
#define NAU8325_ADC_GAIN_L_MAX	0xc1
#define NAU8325_ADC_GAIN_L_MASK	(0xff << NAU8325_ADC_GAIN_L_SFT)
#define NAU8325_ADC_GAIN_R_SFT	0
#define NAU8325_ADC_GAIN_R_MAX	0xc1
#define NAU8325_ADC_GAIN_R_MASK	0xff

/* BOOST_CTRL1 (0x17) */
#define NAU8325_BSTLIMIT_SFT		8
#define NAU8325_BSTLIMIT_MAX		0x3f
#define NAU8325_BSTLIMIT_MASK	(0x3f << NAU8325_BSTLIMIT_SFT)
#define NAU8325_BSTMARGIN_SFT	0
#define NAU8325_BSTMARGIN_MAX	0x3f
#define NAU8325_BSTMARGIN_MASK	0x3f

/* BOOST_CTRL2 (0x18) */
#define NAU8325_TC_SFT			15
#define NAU8325_TC_EN			(0x1 << NAU8325_TC_SFT)
#define NAU8325_BSTHOLD_SFT		7
#define NAU8325_BSTHOLD_MASK		(0xf << NAU8325_BSTHOLD_SFT)
#define NAU8325_BSTSTEPTIME_SFT	4
#define NAU8325_BSTSTEPTIME_MASK	(0x7 << NAU8325_BSTSTEPTIME_SFT)
#define NAU8325_BSTDELAY_MASK	0xf

/* DSP_CORE_CTRL2 (0x1a) */
#define NAU8325_DAC_SEL_DSP_SFT	5
#define NAU8325_DAC_SEL_DSP_OUT	(0x1 << NAU8325_DAC_SEL_DSP_SFT)
#define NAU8325_DSP_RUNSTALL_SFT	4
#define NAU8325_DSP_RUNSTALL		(0x1 << NAU8325_DSP_RUNSTALL_SFT)

/* ADC_RATE (0x28) */
#define NAU8325_I2S_MODE_SFT		15
#define NAU8325_I2S_MODE		(0x1 << NAU8325_I2S_MODE_SFT)
#define NAU8325_UNSIGN_IV_SFT	8
#define NAU8325_UNSIGN_IV		(0x1 << NAU8325_UNSIGN_IV_SFT)
#define NAU8325_ADC_SYNC_DOWN_SFT	0
#define NAU8325_ADC_SYNC_DOWN_MASK	0x3
#define NAU8325_ADC_SYNC_DOWN_32	0
#define NAU8325_ADC_SYNC_DOWN_64	1
#define NAU8325_ADC_SYNC_DOWN_128	2

/* DAC_CTRL1 (0x29) */
#define NAU8325_DAC_OVERSAMPLE_SFT	0
#define NAU8325_DAC_OVERSAMPLE_MASK	0x7
#define NAU8325_DAC_OVERSAMPLE_64	0
#define NAU8325_DAC_OVERSAMPLE_256	1
#define NAU8325_DAC_OVERSAMPLE_128	2
#define NAU8325_DAC_OVERSAMPLE_32	4

/* ALC_CTRL1 (0x2c) */
#define NAU8325_ALC_MAXGAIN_SFT	5
#define NAU8325_ALC_MAXGAIN_MAX	0x7
#define NAU8325_ALC_MAXGAIN_MASK	(0x7 << NAU8325_ALC_MAXGAIN_SFT)
#define NAU8325_ALC_MINGAIN_SFT	1
#define NAU8325_ALC_MINGAIN_MAX	4
#define NAU8325_ALC_MINGAIN_MASK	(0x7 << NAU8325_ALC_MINGAIN_SFT)
#define NAU8325_ALC_GAIN_SEL_SFT	0
#define NAU8325_ALC_GAIN_SEL_MODE	1

/* ALC_CTRL2 (0x2d) */
#define NAU8325_ALC_DCY_SFT		12
#define NAU8325_ALC_DCY_MAX		0xb
#define NAU8325_ALC_DCY_MASK		(0xf << NAU8325_ALC_DCY_SFT)
#define NAU8325_ALC_ATK_SFT		8
#define NAU8325_ALC_ATK_MAX		0xb
#define NAU8325_ALC_ATK_MASK		(0xf << NAU8325_ALC_ATK_SFT)
#define NAU8325_ALC_HLD_SFT		4
#define NAU8325_ALC_HLD_MAX		0xa
#define NAU8325_ALC_HLD_MASK		(0xf << NAU8325_ALC_HLD_SFT)
#define NAU8325_ALC_LVL_SFT		0
#define NAU8325_ALC_LVL_MAX		0xf
#define NAU8325_ALC_LVL_MASK		0xf

/* ALC_CTRL3 (0x2e) */
#define NAU8325_ALC_EN_SFT		15
#define NAU8325_ALC_EN			(0x1 << NAU8325_ALC_EN_SFT)
#define NAU8325_LIM_MDE_SFT		12
#define NAU8325_LIM_MDE_MASK		(0x7 << NAU8325_LIM_MDE_SFT)
#define NAU8325_VBAT_THLD_SFT	5
#define NAU8325_VBAT_THLD_MAX	0x1f
#define NAU8325_VBAT_THLD_MASK	(0x1f << NAU8325_VBAT_THLD_SFT)
#define NAU8325_AUTOATT_EN_SFT	4
#define NAU8325_AUTOATT_EN		(0x1 << NAU8325_AUTOATT_EN_SFT)

/* TEMP_COMP_CTRL (0x30) */
#define NAU8325_TEMP_COMP_ACT2_MASK 0xff

/* LPF_CTRL (0x33) */
#define NAU8325_LPF_IN1_EN_SFT	15
#define NAU8325_LPF_IN1_EN		(0x1 << NAU8325_LPF_IN1_EN_SFT)
#define NAU8325_LPF_IN1_TC_SFT	11
#define NAU8325_LPF_IN1_TC_MASK	(0xf << NAU8325_LPF_IN1_TC_SFT)
#define NAU8325_LPF_IN2_EN_SFT	10
#define NAU8325_LPF_IN2_EN		(0x1 << NAU8325_LPF_IN2_EN_SFT)
#define NAU8325_LPF_IN2_TC_SFT	6
#define NAU8325_LPF_IN2_TC_MASK	(0xf << NAU8325_LPF_IN2_TC_SFT)

/* CLK_DET_CTRL (0x40) */
#define NAU8325_APWRUP_SFT		15
#define NAU8325_APWRUP_EN		(0x1 << NAU8325_APWRUP_SFT)
#define NAU8325_CLKPWRUP_SFT		14
#define NAU8325_CLKPWRUP_EN		(0x1 << NAU8325_CLKPWRUP_SFT)
#define NAU8325_PWRUP_DFT_SFT	13
#define NAU8325_PWRUP_DFT		(0x1 << NAU8325_PWRUP_DFT_SFT)
#define NAU8325_REG_SRATE_SFT	10
#define NAU8325_REG_SRATE_MASK	(0x7 << NAU8325_REG_SRATE_SFT)
#define NAU8325_REG_ALT_SRATE_SFT	9
#define NAU8325_REG_ALT_SRATE_EN	(0x1 << NAU8325_REG_ALT_SRATE_SFT)
#define NAU8325_REG_DIV_MAX		0x1

/* BIAS_ADJ (0x60) */
#define NAU8325_BIAS_VMID_SEL_SFT	4
#define NAU8325_BIAS_VMID_SEL_MASK	(0x3 << NAU8325_BIAS_VMID_SEL_SFT)

/* ANALOG_CONTROL_1 (0x61) */
#define NAU8325_ISEN_SFT		14
#define NAU8325_ISEN_MASK		(0x3 << NAU8325_ISEN_SFT)
#define NAU8325_ADCRSTEN_SFT		12
#define NAU8325_ADCRSTEN_MASK	(0x3 << NAU8325_ADCRSTEN_SFT)
#define NAU8325_VSEN_SFT		10
#define NAU8325_VSEN_MASK		(0x3 << NAU8325_VSEN_SFT)
#define NAU8325_ADCEN_SFT		8
#define NAU8325_ADCEN_MASK		(0x3 << NAU8325_ADCEN_SFT)
#define NAU8325_DACCLKEN_SFT		6
#define NAU8325_DACCLKEN_MASK	(0x3 << NAU8325_DACCLKEN_SFT)
#define NAU8325_DACEN_SFT		4
#define NAU8325_DACEN_MASK		(0x3 << NAU8325_DACEN_SFT)
#define NAU8325_BIASEN_SFT		2
#define NAU8325_BIASEN_MASK		(0x3 << NAU8325_BIASEN_SFT)
#define NAU8325_VMIDEN_MASK		0x3

/* ANALOG_CONTROL_2 (0x62) */
#define NAU8325_CLASSDEN_SFT		4
#define NAU8325_CLASSDEN_MASK	(0x3 << NAU8325_CLASSDEN_SFT)
#define NAU8325_PDVMDFST_SFT		2
#define NAU8325_PDVMDFST_MASK	(0x3 << NAU8325_PDVMDFST_SFT)
#define NAU8325_BSTEN_MASK		0x3

/* ANALOG_CONTROL_3 (0x63) */
#define NAU8325_DACREFCAP_SFT	4
#define NAU8325_DACREFCAP_MASK	(0x3 << NAU8325_DACREFCAP_SFT)

/* ANALOG_CONTROL_4 (0x64) */
#define NAU8325_RECV_MODE_SFT	15
#define NAU8325_RECV_MODE		(0x1 << NAU8325_RECV_MODE_SFT)
#define NAU8325_AUTOATTMIN_SFT	14
#define NAU8325_AUTOATTMIN_MASK	(0x1 << NAU8325_AUTOATTMIN_SFT)
#define NAU8325_AUTOATTMIN_12DB	(0x0 << NAU8325_AUTOATTMIN_SFT)
#define NAU8325_AUTOATTMIN_0DB	(0x1 << NAU8325_AUTOATTMIN_SFT)
#define NAU8325_CLASSD_SLEWP_SFT	3
#define NAU8325_CLASSD_SLEWP_MASK	(0x7 << NAU8325_CLASSD_SLEWP_SFT)
#define NAU8325_CLASSD_SLEWN_MASK	0x7

/* ANALOG_CONTROL_5 (0x65) */
#define NAU8325_MCLK_RANGE_SFT	2
#define NAU8325_MCLK_RANGE_EN	(0x1 << NAU8325_MCLK_RANGE_SFT)
#define NAU8325_MCLK8XEN_SFT		1
#define NAU8325_MCLK8XEN_EN		(0x1 << NAU8325_MCLK8XEN_SFT)
#define NAU8325_MCLK4XEN_EN		0x1

/* ANALOG_CONTROL_6 (0x66) */
#define NAU8325_BSTRADJ_SFT		12
#define NAU8325_BSTRADJ_MASK		(0x7 << NAU8325_BSTRADJ_SFT)
#define NAU8325_BSTSLEWPOFF_SFT	10
#define NAU8325_BSTSLEWPOFF_MASK	(0x3 << NAU8325_BSTSLEWPOFF_SFT)
#define NAU8325_BSTSLEWPON_SFT	8
#define NAU8325_BSTSLEWPON_MASK	(0x3 << NAU8325_BSTSLEWPON_SFT)
#define NAU8325_BSTSLEWNON_SFT	6
#define NAU8325_BSTSLEWNON_MASK	(0x3 << NAU8325_BSTSLEWNON_SFT)
#define NAU8325_BSTSLEWNOFF_SFT	4
#define NAU8325_BSTSLEWNOFF_MASK	(0x3 << NAU8325_BSTSLEWNOFF_SFT)
#define NAU8325_BSTIPDR_MASK		0x7

/* ANALOG_CONTROL_7 (0x68) */
#define NAU8325_ADCGAIN_SFT		9
#define NAU8325_ADCGAIN_MASK	(0x3 << NAU8325_ADCGAIN_SFT)
#define NAU8325_VREFBG_SFT		6
#define NAU8325_VREFBG_EN		(0x1 << NAU8325_VREFBG_SFT)
#define NAU8325_MU_HALF_RANGE_SFT	3
#define NAU8325_MU_HALF_RANGE_EN	(0x1 << NAU8325_MU_HALF_RANGE_SFT)
#define NAU8325_MCLK16XEN_SFT	2
#define NAU8325_MCLK16XEN_EN		(0x1 << NAU8325_MCLK16XEN_SFT)


/* ANALOG_CONTROL_8 (0x6b) */
#define NAU8325_VBAT_PCL_SFT		11
#define NAU8325_VBAT_PCL_MAX		0x1f
#define NAU8325_VBAT_PCL_MASK	(0x1f << NAU8325_VBAT_PCL_SFT)
#define NAU8325_VBAT_THD_SFT		4
#define NAU8325_VBAT_THD_MAX	0xf
#define NAU8325_VBAT_THD_MASK	(0xf << NAU8325_VBAT_THD_SFT)

/* ANALOG_CONTROL_9 (0x6c) */
#define NAU8325_VBAT_CURLMT_MASK	0x1f

/* RDAC (0x73) */
#define NAU8325_DACVREFSEL_SFT	2
#define NAU8325_DACVREFSEL_MASK	(0x3 << NAU8325_DACVREFSEL_SFT)

/* BOOST (0x76) */
#define NAU8325_STG2_SEL_SFT		14
#define NAU8325_STG2_SEL_CLASSA	(0x1 << NAU8325_STG2_SEL_SFT)

/* FEPGA (0x77) */
#define NAU8325_CURR_TRIM_SFT	8
#define NAU8325_CURR_TRIM_MAX	0x7
#define NAU8325_CURR_TRIM_MASK	(0x7 << NAU8325_CURR_TRIM_SFT)
#define NAU8325_CMLCK_ENB_SFT	7
#define NAU8325_CMLCK_ENB		(0x1 << NAU8325_CMLCK_ENB_SFT)

/* POWER_UP_CONTROL (0x7f) */
#define NAU8325_PGA_GAIN_SFT		4
#define NAU8325_PGA_GAIN_MAX	0x4
#define NAU8325_PGA_GAIN_MASK	(0x7 << NAU8325_PGA_GAIN_SFT)


#define NAU8325_CODEC_DAI "nau8325-hifi"


struct nau8325 {
	struct device *dev;
	struct regmap *regmap;
	struct snd_soc_dapm_context *dapm;
	int irq;
	int mclk;
	int fs;
	int vref_impedance;
	int dac_vref;
	int sar_voltage;
	int sar_compare_time;
	int sar_sampling_time;
	int clock_detection;
	int clock_det_data;
	int temp_compensation;
	int boost_delay;
	int boost_convert_enable;
	int boost_target_limit;
	int boost_margin;
	int normal_iis_data;
	int alc_enable;
};

struct nau8325_src_attr {
	int param;
	unsigned int val;
};

enum {
	NAU8325_MCLK_FS_RATIO_256,
	NAU8325_MCLK_FS_RATIO_400,
	NAU8325_MCLK_FS_RATIO_500,
	NAU8325_MCLK_FS_RATIO_NUM,
};

struct nau8325_srate_attr {
	int fs;
	int range;
	bool max;
	unsigned int mclk_src[NAU8325_MCLK_FS_RATIO_NUM];
	int adc_div;
};

struct nau8325_osr_attr {
	unsigned int osr;
	unsigned int clk_src;
};

#endif /* __NAU8325_H__ */
